? semiconductor components industries, llc, 2012 april, 2012 ? rev. 0 1 publication order number: nbvspa013/d nbvspa013 2.5 v, 212.00 mhz lvds voltage-controlled clock oscillator (vcxo) pureedge product series the nbvspa013 voltage ? controlled crystal oscillator (vcxo) is designed to meet today?s requirements for 2.5 v lvds clock generation applications. these devices use a high q fundamental mode crystal and phase locked loop (pll) multiplier to provide 212.00 mhz with a pullable range of 100 ppm and a frequency stability of 50 ppm. the silicon ? based pureedge products design provides users with exceptional frequency stability and reliability. they produce an ultra low jitter and phase noise lvds differential output. the nbvspa013 is a member of on semiconductor?s pureedge clock family that provides accurate and precision clock generation solutions. available in the industry standard 5.0 x 7.0 x 1.8 mm smd (clcc) package on 16 mm tape and reel in quantities of 1,000 and 100. features ? lvds differential output ? uses high q fundamental mode crystal ? ultra low jitter and phase noise ? 0.5 ps (12 khz ? 20 mhz) ? pullable range minimum of 100 ppm ? frequency stability of 50 ppm ? control voltage with positive slope ? voltage control linearity of 10% ? hermetically sealed ceramic smd packages of size 5.0 x 7.0 x 1.8 mm ? operating range: 2.5 v 5% ? these devices are pb ? free and are rohs compliant applications ? networking ? networking base stations ? broadcasting http://onsemi.com marking diagrams a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package 6 pin clcc ln suffix case 848ab nbvspa013 212.0000 awlyywwg see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information
nbvspa013 http://onsemi.com 2 figure 1. simplified logic diagram pll clock multiplier crystal gnd oe v c clk clk v dd 654 123 lvds oe v c gnd clk v dd clk 1 2 3 6 5 4 figure 2. pin connections (top view) table 1. pin description pin no. symbol i/o description 1 v c (note 1) analog input analog control voltage input pin that adjusts output oscillation frequency. f 0 =v c = 1.25 v 2 oe lvttl/lvcmos control input output enable pin. when left floating pin defaults to logic high and output is active. see oe pin description table 2. 3 gnd power supply ground at 0 v. electrical and case ground. 4 clk lvds output non ? inverted clock output. typically loaded with 100 receiver termination resistor across differential pair. 5 clk lvds output inverted clock output. typically loaded with 100 receiver termination resistor across differential pair. 6 v dd power supply positive power supply voltage. voltage should not exceed 2.5 v 5%. 1. control voltage has a positive slope with a typical linearity of 10%; v c = 1.25 v 1 v. table 2. output enable tri ? state function oe pin output pins open active high level active low level high z table 3. attributes characteristic value input default state resistor 170 k esd protection human body model machine model 2 kv 200 v meets or exceeds jedec standard eia/jesd78 ic latchup test
nbvspa013 http://onsemi.com 3 table 4. maximum ratings symbol parameter condition 1 condition 2 rating units v dd positive power supply gnd = 0 v 4.6 v v in control input (v c and oe) v in v dd + 200 mv v in gnd ? 200 mv v i osc output short circuit current clk to clk clk or clk to gnd continuous continuous 12 24 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 55 to +120 c t sol wave solder see figure 5 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 5. dc characteristics (v dd = 2.5 v 5%, gnd = 0 v, t a = ? 40 c to +85 c) (note 2) symbol characteristic conditions min. typ. max. units i dd power supply current 75 100 ma v ih oe and fsel input high voltage 2000 v dd mv v il oe and fsel input low voltage gnd ? 300 800 mv i ih input high current oe ? 100 +100 a i il input low current oe ? 100 +100 a v od change in magnitude of v od for complementary output states (note 3) 0 1 25 mv v os offset voltage 1125 1375 mv v os change in magnitude of v os for complementary output states (note 3) 0 1 25 mv v oh output high voltage 1425 1600 mv v ol output low voltage 900 1075 mv v od differential output voltage 250 450 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 ifpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. measurement taken with outputs terminated with 100 ohm across differential pair. see figure 4. 3. parameter guaranteed by design verification not tested in production.
nbvspa013 http://onsemi.com 4 table 6. ac characteristics (v dd = 2.5 5%, gnd = 0 v, t a = ? 40 c to +85 c) (note 4) symbol characteristic conditions min. typ. max. unit f clkout output clock frequency nbvspa013 212.00 mhz f frequency stability (note 5) 50 ppm t jit ( ) rms phase jitter 12 khz to 20 mhz 0.4 0.9 ps t jitter cycle to cycle, rms 1000 cycles 3 8 ps cycle to cycle, peak ? to ? peak 1000 cycles 15 30 ps period, rms 10,000 cycles 2 4 ps period, peak ? to ? peak 10,000 cycles 10 20 ps t oe/od output enable/disable time 200 ns f p crystal pullability (note 6) 0 v v c v dd 100 ppm v c(bw) control voltage bandwidth ? 3 db 20 khz t duty_cycle output clock duty cycle (measured at cross point) 45 50 55 % t r output rise time (20% and 80%) 245 400 ps t f output fall time (80% and 20%) 245 400 ps t start start ? up time 1 5 ms aging 1 st year 3 ppm every year after 1 st 1 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 ifpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. measurement taken with outputs terminated with 100 ohm across differential pair. see figure 4. 5. parameter guarantees 10 years of aging. includes initial stability at 25 c, shock, vibration and first year aging. 6. gain transfer is positive with a rate of 130 ppm/v. table 7. phase noise performance for nbvspa013 parameter characteristic condition 212.00 mhz unit noise output phase ? noise performance 100 hz of carrier ? 82 dbc/hz 1 khz of carrier ? 11 0 dbc/hz 10 khz of carrier ? 122 dbc/hz 100 khz of carrier ? 123 dbc/hz 1 mhz of carrier ? 132 dbc/hz 10 mhz of carrier ? 160 dbc/hz
nbvspa013 http://onsemi.com 5 figure 3. typical phase noise plot at 212.00 mhz
nbvspa013 http://onsemi.com 6 table 8. reliability compliance parameter standard method shock ? std ? 833, method 2002, condition b ? std ? 833, method 2003 ? std ? 833, method 2007, condition a ? std ? 202, method 215 ? std ? 833, method 1011, condition a c per ipc/jedec j ? std ? 020d figure 4. typical termination for output driver and device evaluation driver device receiver device clk d clk d z o = 50 z o = 50 100 nbvspa013 260 217 175 150 temperature ( c) temp. 260 c 20 ? 40 sec. max. time 60 180 sec. 3 c/sec. max. cooling 6 c/sec. max. 60 150 sec. reflow peak pre ? heat ramp ? up figure 5. recommended reflow soldering profile table 9. ordering information device output frequency (mhz) package shipping ? 5.0 x 7.0 x 1.8 mm NBVSPA013LN1TAG 212.0000 clcc ? 6, pb ? free 1000 / tape & reel nbvspa013lnhtag 212.0000 clcc ? 6, pb ? free 100 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d
nbvspa013 http://onsemi.com 7 package dimensions 6 pin clcc, 7x5, 2.54p case 848ab issue c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. a b e d bottom view b e 6x 0.10 b 0.05 a c c 0.15 c terminal 1 indicator top view a a1 a3 0.10 c c seating plane side view l 6x 1 2 5 6 d3 dim a min nom max millimeters 1.70 1.80 1.90 a1 0.70 ref b 1.30 1.40 1.50 d1 6.17 6.20 6.23 d2 6.66 6.81 6.96 e1 4.37 4.40 4.43 r 0.70 ref l 1.17 1.27 1.37 a2 0.36 ref a3 0.08 0.10 0.12 d 7.00 bsc d3 5.08 bsc e 5.00 bsc e2 4.65 4.80 4.95 e3 3.49 bsc e 2.54 bsc d1 e1 d2 e2 a2 3 4 e3 r 4x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* pitch 2.54 1.50 6x 5.06 1.50 6x dimension: millimeters h h 1.80 ref on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. nbvspa013/d pureedge is a trademark of semiconductor components industries, llc (scillc). publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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